Demand for integrated circuits (ICs) in portable electronic applications has motivated greater levels of semiconductor device integration. Many advanced semiconductor devices in development leverage non-silicon semiconductor materials, some of which offer the potential of high breakdown voltages. The group III-nitride (III-N) material system shows particular promise for high voltage and high frequency applications like power management ICs and RF power amplifiers.
GaN transistors fabricated on Si substrates designed for a high breakdown voltage have conventionally had lateral device architectures. A conventional lateral GaN power transistor 101 is illustrated in FIG. 1, for example. Transistor 101 includes a GaN layer 110 disposed over a (111) surface of a silicon substrate 105. GaN layer 110 is typically 2-5 μm thick. A polarization layer 120 is grown over GaN layer 110 forming a two-degree electron gas (2DEG) 111 spanning a lateral spacing L1 between gate electrode 130, source electrode 140, and drain electrode 150. For high breakdown voltage (e.g., >100V) applications, lateral gate-drain pitch L1 may be over 5 μm. Such a large lateral dimension is often necessitated by poor passivation of the III-N surface by the overlying dielectric layer 180, which can lead to premature breakdown in the presence of electric fields that increase in strength with decreasing L1. With the lateral gate-drain pitch L1 then unable to shrink for a given breakdown voltage specification, opportunities for scaling the source-drain pitch L2 are limited in such devices.
III-N power transistor architectures that enable smaller source-drain pitch for a given minimum breakdown voltage, and are scalable would be advantageous for both discrete III-N power devices and SoC applications (e.g., power management IC s and RF power amplifiers) where III-N power transistors are integrated with other devices, such as silicon-based logic transistors.